The invention relates to a semiconductor integrated circuit for supplying a plurality of potentials to macro cells.
With reduction in dimensions of devices, more and more elements tend to be mounted on a semiconductor chip. The overall functionality of a system is implemented by providing on a semiconductor chip a multiplicity of macro cells each having a plurality of elements such as logic elements, memory elements, and analog elements in a prescribed region.
An external terminal or an internal power supply circuit of the chip is used to supply power to these macro cells. In order to evenly apply a power supply current to the multiplicity of macro cells, power supply lines are provided all over the chip by using upper layer lines and power is supplied from the power supply lines to the macro cells.
In a conventional semiconductor integrated circuit, macro cell power supply lines are provided in a ring shape in the outer periphery of the macro cells so that the macro cell power supply lines can be easily connected to chip-level power supply lines extending in the horizontal and vertical directions of the macro cells (e.g., see “System LSI Design, LSI Design, Lecture Material,” SoC (System on a Chip) Design Technology, STARC (Semiconductor Technology Academic Research Center) Endowed Chair in 2002, Waseda University, Chapter 6, Layout Design 2, p. 34). In recent semiconductor integrated circuits having multiple semiconductor wiring layers, macro cell power supply lines are arranged in stripes on the macro cells.
FIG. 16 is a block diagram showing the structure of power supply lines of a conventional semiconductor integrated circuit. A macro cell 100 of FIG. 16 includes a plurality of logic elements and is formed in fourth and lower wiring layers. Macro cell outer peripheral power supply lines 110, 111, 120, and 121 are arranged in a ring shape in the outer periphery of the macro cell 100.
The macro cell outer peripheral power supply lines 110 extend in the vertical direction and supply a potential level VDD to the macro cell 100. The macro cell outer peripheral power supply lines 111 extend in the vertical direction and supply a potential level VSS to the macro cell 100. The macro cell outer peripheral power supply lines 120 extend in the horizontal direction and supply a potential level VDD to the macro cell 100. The macro cell outer peripheral power supply lines 121 extend in the horizontal direction and supply a potential level VSS to the macro cell 100.
The macro cell outer peripheral power supply lines 110, 111 are formed in a fourth wiring layer. The macro cell outer peripheral power supply lines 120, 121 are formed in a third wiring layer. The macro cell outer peripheral power supply lines 110, 120 are connected to each other through contacts formed at the intersections of the macro cell outer peripheral power supply lines 110, 120. Similarly, the macro cell outer peripheral power supply lines 111, 121 are connected to each other through contacts formed at the intersections of the macro cell outer peripheral power supply lines 111, 121.
The macro cell 100 receives a potential level VDD and a potential level VSS by connecting the macro cell outer peripheral power supply lines 110, 111, 120, and 121 with macro cell internal power supply lines that extend in the vertical or horizontal direction. The macro cell outer peripheral power supply lines 110, 111, 120, and 121 have such a wiring width that the macro cell outer peripheral power supply lines 110, 111, 120, and 121 can supply a current that is consumed in the macro cell 100.
Chip-level power supply lines 130, 131, 140, and 141 are formed in a fifth or higher wiring layer that is located higher than the layers of the macro cell 100 and the macro cell outer peripheral power supply lines 110, 111, 120, and 121. The chip-level power supply lines 130, 131 extend in the horizontal or vertical direction and supply a potential level VDD to the macro cell outer peripheral power supply lines 110 or 120. The chip-level power supply lines 140, 141 extend in the horizontal or vertical direction and supply a potential level VSS to the macro cell outer peripheral power supply lines 111 or 121.
Macro cell outer peripheral power supply lines need to have a wiring width equal to or larger than a wiring width corresponding to a current that is consumed in a macro cell. Even a macro cell having a small area needs a large current in the case where a wiring capacitance of an output is large and the macro cell has an output buffer having large driving capability, in the case of high speed operation, and the like. In these cases, the macro cell outer peripheral power supply lines have a large wiring width. Therefore, even when the area of the macro cell itself is small, the overall area including the power supply lines becomes large.
As described above, a conventional semiconductor integrated circuit has macro cell outer peripheral power supply lines in the outer periphery of each macro cell. Therefore, when a large current need to be supplied to a macro cell, the overall area of the macro cell including the power supply lines is increased and the area of the semiconductor integrated circuit is increased accordingly.
Especially in resent semiconductor integrated circuits, reduction in wiring dimensions has caused an increase in line-to-line capacitance and wiring resistance, and an operating frequency of the circuits has been increasing. Therefore, the wiring width of the macro cell outer peripheral power supply lines need to be increased in order to supply a required power supply current to the macro cells.
Moreover, lead-in wirings from the macro cell outer peripheral power supply lines to the macro cells are also required. Such lead-in wirings need to be provided in consideration of factors such as a lead-in wiring resistance, a via connection resistance, an allowable current amount for assuring reliability, and an IR (current-resistance) drop. Therefore, the number of lead-in wirings, the lead-in wiring width, and the number of connection vias need to be increased.
Power supply lines for supplying a substrate potential are also required for circuit elements for controlling a substrate potential. However, connection between such circuit elements and chip-level substrate power supply lines has been getting difficult.